In an article entitled "A Substrate-Plate Trench-Capacitor (SPT) Memory Cell for Dynamic RAM's", IEEE Journal of Solid State Circuits, Vol. SC-21, No. 5, October 1986, Nicky Chau-Chun Lu et al. describe a dynamic random access memory (DRAM) cell employing a trench capacitor with a grounded substrate plate. A cell array is located inside of a well with the trench capacitor extending from a planar surface through the well and into a heavily doped substrate. Polysilicon deposited within the trench is connected to a source region of a transfer device. The polysilicon functions as a charge storage node while the bulk silicon surrounding the trench serves as a capacitor plate electrode.
In this and other trench capacitor devices, such as those described below, the total charge storing capacity of the trench capacitor is a function of the area of the trench inside walls. However, as devices are scaled downwards in size in order to increase packing density and memory capacity this area is also reduced. As a result, existing trench capacitor fabrication techniques place a lower limit on the size of memory cells and, thus, also on a maximum memory capacity that can be realized within a specified integrated circuit area.
U.S. Patents that relate to various aspects of trench capacitor technology include the following which are listed in chronological order.
In U.S. Pat. No. 4,577,395, issued 3/25/86, and entitled, "Method of Manufacturing Semiconductor Memory Device Having Trench Memory Capacitor", T. Shibata discloses a semiconductor substrate that is selectively etched so as to form a first groove in an element isolation region. An insulation film is buried in the first groove. The semiconductor substrate is further selectively etched and the insulation film buried in the first groove is employed as an etching mask so as to form second grooves in the respective memory capacitor forming regions.
In commonly assigned U.S. Pat. No. 4,704,368, issued 11/3/87, and entitled, "Method of Making Trench-Incorporated Monolithic Semiconductor Capacitor and High Density Dynamic Memory Cells Including the Capacitor", Goth et al. disclose a capacitor formed by an isolated region of silicon material which functions as a first capacitor plate, a doped polysilicon layer provided on the vertical walls of a mesa serving as a second capacitor plate, and a thin dielectric layer interposed between the two plates.
In U.S. Pat. No. 4,734,384 issued 3/29/88, and entitled, "Process for Manufacturing Semiconductor Memory Device", Tsuchiya discloses a memory cell having a capacitor element that utilizes a trench or moat formed in a semiconductor substrate, and a MISFET. One of the electrodes of the capacitor element is connected to the MISFET at the side wall of the upper end of the moat for forming the capacitor element. The electrode is connected in self alignment with a semiconductor region which serves as either the source or drain of the MISFET.
In U.S. Pat. No. 4,784,969 issued 11/15/88, and entitled, "Method of Manufacturing a Semiconductor Memory Device", Nitayama discloses the steps of forming a groove in a capacitor-forming region of a semiconductor substrate and providing a capacitor electrode covering the inner surface of the groove and a first contact hole. An interconnection electrode layer insulating film is formed over surfaces of the capacitor electrode and an interconnection electrode, forming a gate insulating film on a portion of the surface of the semiconductor substrate which lies between the capacitor electrode and interconnection electrode.
In U.S. Pat. No. 4,786,954 issued 11/22/88, and entitled, "Dynamic Ram Cell With Trench Surrounded Switching Element", Morie et al. disclose memory cells including at least one capacitor and a trench formed from one major surface of the semiconductor substrate so as to surround at least one memory cell.
In U.S. Pat. No. 4,798,794, issued 1/17/89, and entitled, "Method for Manufacturing Dynamic Memory Cell", Ogura et al. disclose an insulating film for capacitor formation formed on the inner surface of a hole within a P+ layer (first conductive layer) formed over a P- substrate. A conductive layer acting as a capacitor electrode is formed on the insulating film. With the conductive layer as a mask, an N type is doped into the P+ layer to form a second conductive layer. A MOS transistor is formed in a surface portion of the second conductive layer.
In U.S. Pat. No. 4,801,989 issued 1/31/89, and entitled, "Dynamic Random Access Memory Having Trench Capacitor With Polysilicon Lined Lower Electrode", Taguchi discloses a dynamic random access memory having a trench capacitor. A first conductive layer is formed on all inner surfaces of the trench except for a region adjacent to the opening portion of the trench. A dielectric layer is formed on the first conductive layer exposed in the trench and the surface of the semiconductor substrate, and a second conductive layer of another conduction type is filled in the trench through the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer constitute the storage capacitor.
In U.S. Pat. No. 4,803,535 issued 2/7/89, and entitled, "Dynamic Random Access Memory Trench Capacitor", Taguchi discloses a trench capacitor that includes a semiconductor substrate, a trench formed in the substrate, and an insulating layer formed on an inner surface of the trench and having a bottom opening. A first conductive layer is formed at the bottom opening position and on the insulating layer, the first conductive layer being ohmically connected to the semiconductor substrate at the bottom opening. The device includes further a dielectric layer formed on the first conductive layer and a second conductive layer formed on the dielectric layer so as to fill the trench. The first conductive layer, the dielectric layer, and the second conductive layer constitute a charge storage capacitor. A MIS transistor is formed in the semiconductor substrate such that the second conductive layer is ohmically connected to a source or drain region of the transistor.
In U.S. Pat. No. 4,829,017, issued 5/9/89, entitled "Method for Lubricating (sic) a High Capacity DRAM Cell" S. Mahli discloses a trench capacitor that underlies a transistor 30. A capacitor plate 52 is a core enclosed annularly by dielectric insulation 54. Another semiconductor capacitor plate 56 encircles the dielectric isolation. The core plate 52 is of an opposite conductivity type (N-type) than the outer surrounding plate 56 (P-type).
In U.S. Pat. No. 4,958,318, issued 9/18/90, and entitled, "Sidewall Capacitor Dram Cell", Harari discloses a dynamic RAM that is said to be provided with enhanced charge storage capacity by increasing the surface area between two electrodes of the storage capacitor. A first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. A second electrode is used to partially planarize the surface topology.
IBM Disclosure Bulletin from Vol. 29, No. 3, August 1986, entitled "CMOS Process For Titanium Salicide Bridging of a Trench and Simultaneously Allowing For True Gate Isolation" discloses a CMOS process sequence utilizing salicide to bridge a trench (vertical capacitor) and to also provide for true isolation between a gate, source and drain.
IBM Disclosure Bulletin from Vol. 30, No. 3, August 1987, entitled "Folded Bitline Configuration" discloses in FIG. 1 a memory cell having trench capacitors 1 and 2 in a substrate 3 each connected to a respective source 4 and sharing a common drain junction 5 and a common bitline 6. Word lines 7 and 8 are connected to respective polysilicon transfer gates. The bitline is constructed using one layer of interconnection line among associated cells.
IBM Disclosure Bulletin from Vol. 30, No. 8, January 1988, entitled, "Process To Make Self-Aligned Dynamic Random-Access Memory Cells" discloses trench technology that is used to make small dynamic random-access memory (DRAM) cells. Vertical transistors are formed on trench sidewalls while plate capacitors are formed below the transistors.
IBM Disclosure Bulletin from Vol. 32, No. 3B, August 1989, entitled, "New Process and Layout Enhancement of the SSPT Cell From an Open Bitline to a Folded Bitline Structure" discloses process and layout enhancements which allow a SSPT cell to be laid out in an efficient folded bitline cell structure.
What is not taught by these patents and journal articles, and what is thus an object of the invention to provide, is a method of fabricating a memory cell, and a memory cell fabricated thereby, having a planar access device and an upstanding pedestal structure disposed within a trench for increasing the inner surface area and the capacity of a trench capacitor.